[YOUR NAME] / DFT

Design for Testability / VLSI

Learn DFT from an engineer who does it for a living.

Mock interviews, resume reviews and a project-based cohort for VLSI students and early-career engineers. Build real scan, BIST and JTAG projects with free tools and finish with something you can show.

Book a session See the 6-week cohort

Programs

Three ways to work together

1:1 · 45 to 60 min

DFT mock interview

A live technical interview on scan, ATPG, fault models, MBIST and JTAG, followed by written feedback on what to fix before the real one.

[PRICE] per session

1:1 · async or live

Resume and project review

Line-by-line review of your VLSI resume and projects, with rewritten DFT bullets that say what you built and what it proved.

[PRICE] per review

6 weeks · small batch

DFT project cohort

Weekly live sessions and a hands-on project each week, ending in a capstone you can put on GitHub and on your resume. Batches are capped at 10 to 15 students.

[PRICE] per student

The cohort

Six weeks, one project per week

You learn the concept, build it, and write it up. Each week adds a piece to your portfolio.

WEEK 1

Fault models and testability basics

Build: fault list and fault collapsing exercise

WEEK 2

Scan design and scan chains

Build: scan insertion on a small open-source design

WEEK 3

ATPG concepts and coverage

Build: coverage report and analysis write-up

WEEK 4

BIST and memory BIST

Build: LFSR, MISR and a March test in Verilog

WEEK 5

JTAG and boundary scan

Build: TAP controller with a simulation testbench

WEEK 6

Capstone and resume workshop

Build: GitHub project and interview-ready resume bullets

Hands-on projects

Things you can put on a resume

No commercial EDA licenses needed. Projects run on open-source tools and on designs you write yourself or take from public sources.

LFSR and MISR BIST

Pattern generator and signature analyzer, plus a March algorithm for a small SRAM model.

Verilog · Icarus Verilog · Verilator

JTAG TAP controller

The 16-state FSM, instruction register and boundary scan cells, verified with your own testbench.

Verilog · simulation

Stuck-at fault simulator

Write a fault simulator for gate-level netlists, with fault collapsing and a coverage calculation. A strong interview talking point.

Python or C++

Scan chain debug lab

A netlist with planted defects, such as a broken chain or a shift-mode hold issue. Find them, explain them, fix them.

Netlist analysis · debug

[YOUR PHOTO]

About

[YOUR NAME], Lead DFT Engineer

8 years of hands-on DFT experience across [YOUR AREAS: scan, ATPG, MBIST, JTAG]. I teach the things I wish someone had shown me early: how test actually works on real designs, and how to talk about it in an interview.

Everything I teach uses public tools and public or self-written designs. Nothing comes from any employer. I can't promise a job, but you will leave with working skills and a project you can defend.

Questions

What do I need to know beforehand?

Basic digital logic and some Verilog. If you can read a simple testbench, you are ready.

Do I need paid EDA tools?

No. Projects are built around open-source simulators and your own code.

Will this get me a job?

I can't guarantee placement. You get stronger fundamentals, interview practice and a portfolio project, which is what improves your odds.

When does the next cohort start?

[START DATE]. Sessions run on [DAYS AND TIME, IST]. Book a call below if you want to check fit first.

Ready to build something real?

Book a mock interview or reserve a seat in the next cohort.

Book on Topmate: [YOUR LINK]

Or email [YOUR EMAIL]

[YOUR NAME] · DFT mentoring

Independent of any employer. Views and course content are my own.